1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device involving a capacitor.
2. Discussion of Background
Recently, the MOS dynamic RAM has been integrated and greatly improved. The MOS dynamic RAM is generally represented by a memory cell consisting of one MOS capacitor and one MOSFET. This dynamic RAM (dRAM) has the drawback that the MOS capacitor has a reduced capacitance due to the greater integration and contraction of a memory cell area, thus leading to a decline in the charge capacity. One process of coping with the above-mentioned difficulty is to increase the dielectric constant of the MOS capacitor insulation layer to a level greater than was possible in the past, or make said insulation layer thinner than was possible heretofore. The former process involves the substitution of the SiO.sub.2 insulation layer by a type of Si.sub.3 N.sub.4 or Ta.sub.2 O.sub.5. However, these layers have the drawback that the trap density of carriers is high, thus resulting in an unstable voltage-capacitance characteristic. The latter process is also accompanied with the difficulties that due to the presence of a critical insulation layer thickness which undesirably causes a tunnel current to flow, the insulation layer can be thinned only to an extent of several nm units at most.
Further, a process of effectively broadening the MOS capacitor area set forth, for example, in the Japanese patent disclosure (KOKAI) No. 53-76686 comprises the step of trenching in that region of the substrate surface which constitutes a capacitor and utilizing the side walls of said trench for the above-mentioned object. However, this proposed process is still accompanied with the drawback that difficulties are encountered in forming a deep, fine trench; it is difficult to control the form of said trench; it is also difficult to trench with high reproducibility; and noticeable variations arise in the capacitance.